Best Data CMX300 Specifications download pdf (Page 31)

Functional Description

30-Dec-2010 CM-X300 Reference Guide Rev 1.31 31

Pixel clock frequency is a parameter of the chosen resolution and frames per second, as

well as of the LCD-specific parameters, such as pixel clock wait states at the beginning and

end of each line, the number of line clocks inserted in the beginning and end of each frame.

Here's an example of some common video modes and their corresponding pixel clocks:

http://www.engr.udayton.edu/faculty/jloomis/altera/DE2/vga.html

The LCD data rate required for each plane to support the LCD panel selected for the system

is calculated using this formula:

bps















Pixelper Bits RateRefresh Width Length

= Rate Data

The bits per pixel is the number of bits used in the memory to store each pixel. Memory

organization for pixel depth of 16bpp uses 2 bytes of data per pixel. With overlays enabled,

pixel depth is reduced to 15bpp still using 2 bytes.

The number of 4-beat burst operations (8 bytes/beat) that are generated by the LCD DMA

controller is as follows:

Burst/sec

Rate Data

=Count burst DMA LCD













The time consumed by the LCD refresh operation is then calculated by:

second / Pdma) count burst DMA (LCD merefresh ti LCD 

The value of Pdma is the period in microseconds of LCD DMA four-beat burst, including

SDRAM precharge time. The time remaining within each second after deducting the LCD

refresh time is the time available for instruction and data fetches, hardware accesses, and

memory refresh operations. Use caution when setting system parameters, such as core

frequency, system frequency, memory frequency, and bus arbiter settings to ensure that

LCD FIFOs do not underrun due to bus latencies caused by other internal and external

peripherals. This caution applies especially for interrupt and polled modes that require a

longer time to service.

Benchmarking a real system remains the best way to estimate the LCD subsystem‘s

performance.

3.3.9 USB

3.3.9.1 USB Controllers

The CM-X300 features three USB controllers.

The USB device controller (UDC) is USB 1.1-compliant and supports all standard device

requests issued by any certified USB host controller. This is a full-speed compliant device

(does not support low-speed operation). This controller‘s interface is the CAMI USB2

Interface (only in C624 configurations).

The Universal Serial Bus 2.0 Device Controller (U2DC) supports both high-speed and full-

speed modes. The C624 configuration modules feature the industry standard Universal

Transceiver Macrocell Interface (UTMI), Version 1.05 transceiver for interfacing USB

devices. The transceiver‘s interface is routed to the CAMI USB3 Interface. In the C624M

modules a ULPI transceiver is used instead, connected to the CAMI USB2 Interface.

The Open Host Controller Interface (OHCI) Rev 1.0a-compatible USB host controller

supports both high-speed and full-speed modes. The available interfaces for the host

controller are the CAMI USB2 Interfacein C624 only non-W configuration modules and

the CAMI USB1 Interface in non-W configurations.

For a full description of the USB protocol and its operation, refer to the documents listed in

Table 2 and to Related Documents on page 9.

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 51 52

Comments to this Manuals

No comments

Best Data CMX300 Specifications Page 31

Comments to this Manuals

Related products and manuals for Networking Best Data CMX300