Best Data CMX300 Specifications download pdf (Page 41)

Functional Description

30-Dec-2010 CM-X300 Reference Guide Rev 1.31 41

CM-X300 Signal

Name

Type

Description

SSPTXD3

Synchronous Serial Protocol Transmit Data. Serial data out.

SSPRXD3

Synchronous Serial Protocol Receive Data.Serial data in.

3.3.18.1 SSP Features

The SSP port features are:

 Directly supports Texas Instruments* Synchronous Serial (SSP) and Motorola*

Serial Peripheral Interface (SPI).

 The Inter-IC Sound (I

S) protocol is supported by programming the Programmable

Serial Protocol (PSP). PSP format is only supported for emulation of the I

protocol.

 Data sample sizes can be set to 8, 16, 18 or 32 bits

 One FIFO for transmit data (TXFIFO) and a 2nd, independent, FIFO for receive

data (RXFIFO). For non-packed data mode, the two FIFOs are each 16 rows deep x

32 bits wide for a total of 16 samples.

 FIFO packed mode allows double depth FIFOs if the samples are 8 bits or 16 bits

wide. For packed data mode, both FIFOs are 32 locations deep x 16 bits wide for a

total of 32 samples.

 Master mode and slave mode operation supported

 A maximum serial bit-rate supported of 13 Mbps.

 Receive-without-transmit operation

 Network mode with up to eight time slots for PSP formats, and independent

transmit/receive in any/all/none of the time slots.

3.3.18.2 Turning the SSP Port On

In order to enable SSP function on pins GPIO[85:88], their alternate functions should be

modified in the corresponding configuration registers. A binary value ‗001‘ must be written

into the bits [2:0] of the multi-function pin registers (MFPR) at addresses 0x40E104E8,

0x40E104EC, 0x40E104F0, 0x40E104F4 using a read-modify write access.

3.3.19 PWM Controller

The PWM function enables the control of leading- and falling-edge timing of two output

channels. The edge timing can be set up to run indefinitely or adjusted on the fly to adapt to

variable requirements. Power-saving modes include the ability to stop the internal clock

source (PSCLK_PWM) used to source the PWM and drive the PWM_OUT signals to a

steady high or low state.

The frequency range supporting a 50% duty cycle varies from 198.4 Hz to 6.5 MHz. Other

duty-cycle options depend on the choice of preferred frequency.

Table 45 PWM Signals

CM-X300 Signal

Name

Type

Description

PWM1-OUT

I/O

Pulse-width modulated signal, output of the CPU‘s PWM1 controller. This

pin is used internally by the u-boot when booting the module. It should not

be pulled-up or down by values lower than 100K on the baseboard.

PWM2-OUT

I/O

Pulse-width modulated signal, output of the CPU‘s PWM2 controller

1 2 ... 36 37 38 39 40 41 42 43 44 45 46 ... 51 52

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